The manufacture of integrated circuits (IC), semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto-electronic devices, magneto-optic devices, packaged devices, and the like entails the integration and sequencing of many unit processing steps. As an example, IC manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, lithography, patterning, etching, planarization, implantation, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as speed, power consumption, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, and U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006 which are all herein incorporated by reference.
Typically, during the screening of new materials and processes using HPC methods, each of the regions within the substrate must be tested and the results used to select candidate materials or candidate process conditions for the next level of screening or development. In an R&D environment, the testing, analysis, and evaluation phase can become a bottleneck slowing the rate of discovery and innovation due to long testing times and serial testing protocols. This can lead to the inefficient use of resources, increased costs, and long development times.
Therefore, there is a need to develop systems and methods for increasing the throughput of testing, analysis, and evaluation activities in an R&D environment when using HPC techniques.